Recently, explosive developments in wireless communications have paved the way for communicating data through a portable terminal without limitations of time and place. However, many users have recognized various restrictions of conventional wireless communication services, and those restrictions need to be improved. Representative problems include short maximum call duration of the potable terminal and bad speech quality of the service. The maximum call duration of the portable terminal largely relates to a capacity of battery used in the portable terminal. The batteries that are commonly used are relatively small and light, and can be used for a relatively long time compared to the conventional batteries. However, performance of the batteries does not yet satisfy the user's needs and expectations. This is because a power amplifier module of the communication terminal has a low efficiency. A power consumption of the power amplifier module occupies much of (about 50˜70%) the power consumption of the entire system, such that the low efficiency of the power amplifier module degrades the efficiency of the entire system and largely contributes to shorten the maximum call duration.
The conventional power amplifier used in the wireless terminal is comprised of a typical CLASS AB power amplifier that uses small amount of current at a low power and increases the amount of the current as an input power is raised up. This is an essential method for increasing call duration of the wireless terminal while using minimum power, and is the most widely used method in code division multi access (CDMA) methods in which the linearity is an important performance index.
FIG. 1 is a conventional bias circuit diagram 100 of a power amplifier. A conventional bias circuit 100 of the power amplifier is an emitter follower circuit using a negative feedback circuit. Referring to FIG. 1, the conventional bias circuit 100 includes a feedback transistor Q3 105 that is connected to an emitter of emitter follower stage transistor Q2 103 through a feedback resistor R1 107. A collector of the feedback transistor Q3 105 is connected to a reference voltage source Vref through a reference resistor R2 109. A base of the emitter follower stage transistor Q2 103 is connected to a node N1 113 between the reference resistor R2 109 and the feedback transistor Q3 105. A collector of the emitter follower stage transistor Q2 103 is connected to an operation voltage source Vcc and an emitter of the feedback transistor Q3 105 is grounded. A base of the power amplifier stage transistor Q1 101 is connected to a node N2 111 between the emitter follower stage transistor Q2 103 and the feedback resistor R1 107.
In this conventional bias circuit 100, an amount of current for the power amplifier transistor Q1 101 may be easily controlled using the reference resistor R2 109, and an amount of a feedback current may be controlled using the feedback resistor R1 107. The current feedback by the feedback resistor R1 107 is amplified by the feedback transistor Q2 105. As a result, a current flowing into the base of the emitter follower stage transistor Q2 103 is reduced in amount. Therefore, an amount of current increases according to the input power in the CLASS AB power amplifier may be controlled, such that optimized linearity and efficiency can be determined.
As widely known, an efficiency of the conventional power amplifier is based on a maximum output (about 28 dBm). However, the practical terminals are used at a low output (about 5˜0 dBm) more frequently than at the maximum output. Thus, efficiency at a low output is important to extend duration of the battery, and there have been extensive studies on improvements of the power amplifier module.
A conventional method for improving efficiency of the power amplifier module uses a smart power amplifier having a low power mode and a high power mode. Most of operations of the bias circuit having a mode change type between the low power mode and the high power mode are performed by inserting a circuit for controlling an amount of current of the bias circuit. A switch circuit for subtracting some amount of current is added in a path where the reference current flows.
FIG. 2 is a circuit diagram 200 illustrating this conventional mode change bias circuit. That is, the conventional bias circuit 200 includes a switching transistor Q4 201 connected to a node N1 113 in the bias circuit 100 illustrated in FIG. 1. A collector of the switching transistor Q4 201 is connected to the node N1 113, an emitter thereof is grounded, and a base thereof is connected to a mode selection voltage source Vmode through a resistor R4 205.
According to this conventional bias circuit 200, in a high power mode, a low voltage (e.g., a logic low signal) is applied to the mode selection voltage source Vmode. Accordingly, the switching transistor Q4 201 is turned off so that the bias circuit 200 operates identically as the bias circuit 100 in FIG. 1 and some level of gain and linearity can be maintained to the point of highest power.
To the contrary, in a low power mode, a high voltage (e.g., a logic high signal) is applied to the mode selection voltage source Vmode. Accordingly, the switching transistor Q4 201 is turned on and a portion of the reference current flowing into the reference voltage source Vref of the bias circuit 100 is consumed. Therefore, the reference current flowing into the bias circuit is reduced. This lowers an operation point of the power amplifier transistor Q1 101 and reduces the gain and a current consumption and, as a result, the efficiency of operation in the low power mode can be improved.
Meanwhile, this conventional bias circuit 200, having a mode change type, further includes only the switching transistor Q4 201 as compared to the bias circuit 100 shown in FIG. 1, and uses only one bias circuit. Therefore, if the low power mode is performed in the conventional bias circuit 200 having a mode change bias circuit, the gain increases as the power increases.
Moreover, the mode change to the low power mode compulsorily reduces suitable initial current that should be used in the power amplifier originally because the conventional mode change bias circuit 200 performs the mode change by reducing the reference current. Therefore, in the low power mode, a gm (transconductance) of the power amplifier transistor decreases and thus the gain is reduced. The gain reduced by the decrease of current becomes independent of the initial current of the low power mode in respect of an amount of current as the input power increases. Therefore, the gm increases, and, as a result the gain, is likely to return to the original gain following that of the high power mode, such that a gain variation in power occurs. This gain variation in is an obstacle of reducing the initial current of the low power mode, and degrades an advantage of the low power mode at the boundary point between the low power and the high power.
In addition, if gain flatness is reduced to make the gain variation great, the gain of the power amplifier is not estimated as a fixed value. As a result, various parts for controlling gains according to the output of the power amplifier may not operate normally. This reduction of the gain flatness makes it difficult to set the initial current smaller when the low power mode is designed. The efficiency of low power mode becomes improved as the initial current is set to be as small as possible, but the gain variation in the power increases to restrict the reduction of the initial current.
Moreover, in case of using the convention mode change type bias circuit for reducing the reference current, if the power increases to specific input power, the bias circuit in the low power mode is not driven by a smaller current but by a larger current as if in the high power mode. This is an unavoidable problem due to the characteristics of the CLASS AB power amplifier requiring more current as the input power increases, and a feedback current should be controlled to effectively suppress the increase of the current. However, the conventional mode change bias circuit uses a single bias circuit, such that an amount of the feedback current is not controlled differently between the lower mode and high power mode because the identical bias circuit is used in the low power mode and the high power mode.